Some conventional communication devices reduce interrupts to a CPU by processing data transfer between a memory and an I/O device by dedicated hardware (a DMA control device), and thereby speed up the data transfer. When data transfer such as file transfer is performed, the communication devices are switched from processing by the CPU to data transfer processing by the dedicated hardware after specifying a file size (a data volume). The dedicated hardware executes the data transfer processing of the specified data volume instead of the CPU.
However, there is a problem that the CPU may process a packet that should be processed by the dedicated hardware by mistake due to a timing of switching to the dedicated hardware. For example, a CPU of a transmitting terminal notifies, to a CPU of a receiving terminal, a file size by using a control packet, and file transfer is started by using the dedicated hardware. At this time, if the transmitting-side terminal starts the file transfer before the CPU is switched to the dedicated hardware in the receiving terminal, a packet received before the switching is mistakenly processed in the CPU. If ten packets of data are transmitted from the transmitting terminal, and the first two packets are received and processed by the CPU before the switching, the dedicated hardware receives only eight packets of data that are received after the completion of switching. The dedicated hardware comes into a state of continuously waiting for receiving the two remaining packets.
As described, the conventional technique has a problem in the case that the data transfer is performed with the CPU and the dedicated hardware switched: the CPU may process the packet that should be processed by the dedicated hardware by mistake due to start and end timings of data transfer using the dedicated hardware.